Generally, a pitch of a semiconductor device is shortened according to a decreasing design rule of the semiconductor device, whereby a channel length of a transistor is considerably reduced. Specifically, as a gate length is reduced below 0.13 μm, efforts in connection with shallow junction and super steep channel doping have increased. Specifically, many efforts have been directed to development of fin transistors.
FIGS. 1 to 3 are layout and cross-sectional diagrams, respectively, of a known fin transistor. Referring to FIGS. 1 to 3, in a fin transistor fabricated by a known fabrication method, a contact hole connected to a gate is not allowed to lie on an active area. Thus, the known method has difficulty in fitting a design rule, thereby being disadvantageous in implementing a high degree of integration in a semiconductor device.